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A sidebar to the Apple Macintosh preview published in Byte, issue 2/1984, pp. 32.

Macintosh System Architecture

Inside the Macintosh, hardware and software work together to provide a system capable of supporting high-performance graphics, built-in peripherals, and communication channels to the outside world. From the beginning of the Macintosh project, the product-design goals of small size, light weight, and moderate end-user cost encouraged us to create a low-power, low component-count design. The large number of I/O devices that are built into each unit, combined with our desire for high performance, caused us to explore many alternatives for each aspect of the hardware implementation. A cooperative spirit among the people working on the industrial design, analog electronics, digital electronics, and low-level software resulted in the synthesis of detailed implementations that combined strengths from each group, providing an integrated design solution for all aspects of the product.

Figure 2: A block diagram of the Macintosh hardware
This image can be zoomedFigure 2: A block diagram of the Macintosh hardware
The heart of the Macintosh digital electronics is the MC68000 processor and its memory (both RAM and ROM). In the Macintosh, the data-output lines from the system RAM drive a data bus separate from that used by the rest of the machine (see figure 2). The RAM is triple-ported; this means that the 68000, screen-displaying hardware, and sound-output hardware have periodic access to the address and data buses, so that the video, the sound, and the current 68000 task appear to execute concurrently.

ROM memory connects directly to the system data bus and is used by only the 68000. Much of the system’s time-critical code, such as the low-level graphics primitives, operating-system routines, and user-interface routines, reside in ROM. Macintosh software calls this code through 68000 “line 1010 unimplemented” instructions, which get one of approximately 480 addresses from an address table stored in low memory; this effectively allows the ROM subroutines to function as extensions of the 68000 instruction set. Since the ROM data and address buses are used exclusively by the 68000, ROM is always accessed at the full processor speed of 7.83 MHz; consequently, the ROM can perform as a read-only cache memory.

The 512- by 342-pixel video display appears in memory as a linear array of 10,944 16-bit words of data, with the most significant bit representing the pixel farthest left. Each 512-pixel horizontal line consists of 32 words of data, with bits shifted out at 15.67 MHz (322.68 µs per 512-pixel line) followed by 12 words of horizontal blanking (taking 12.25 µs). The last memory bus cycle of each horizontal line is reserved for sound DMA, where a byte of sound data is fetched from the sound buffer and sent to the sound PWM (pulse-width modulator) for conversion into an analog level. The update rate of the sound channel is then equal to the video horizontal rate, or 22,254.55 Hz. In the vertical direction, 342 active scan lines are followed by a vertical retrace and enough inactive horizontal lines to take up the same time as 28 horizontal lines, providing a vertical retrace time of 1.258 ms. Although screen-memory accesses may occur at any time, a vertical retrace interrupt is generated at the falling edge of the vertical sync pulse to allow screen animation to occur completely synchronous to the video beam movement.

Access to RAM is divided into synchronous time slots, with the 68000 and video circuits sharing alternate word accesses during the live portion of the horizontal video-display line and the sound circuits using the video time slot during the last memory bus cycle of the horizontal line. Although the access to RAM is divided three ways, the 68000’s share is maximized by giving it access to unused cycles during horizontal and vertical blanking. This way, 68000 access to RAM averages to a speed of about 6 MHz.

For high-performance sound generation, a tightly coded routine generates 370 samples of sound data and places them into the sound buffer just after a vertical retrace interrupt. The 68000’s 32-bit registers are used to control pitch with 24 bits of precision, providing each of four possible voices with 16,777,216 possible frequencies. For simpler sounds, a timer in the system’s VIA provides a square wave of programmable pitch. All sounds pass through a software-controlled volume adjustment that creates approximately 20 decibels of total amplitude variation in eight discrete steps.

The Macintosh disk controller is a single LSI (large-scale integration) component referred to as the IWM (“integrated Woz machine”) chip. The device, a one-chip integration of the disk controller originally designed by Steve Wozniak for the Apple II, handles data at 500 kilobits per second. To control the disk drive’s motor speed, a pulse-width modulator located on the digital board allows the disk to move at one of 400 possible disk motor speeds; the PWM is driven from a table in memory in a fashion similar to that of the sound system. By varying the motor speed, we created a more reliable disk drive that puts significantly more data on the same disk.

The Macintosh communications chip, the Zilog 8530 SCC (serial communications controller), provides synchronous and asynchronous data transmission at up to 230.4K bits per second using a self-clocking data format and up to 1 megabit per second using an external clock. The Macintosh’s two serial ports are identical; each provides single-ended or differential signaling and multidrop (party-line) capability.

The 6522 VIA (versatile interface adapter) rounds out the I/O requirements of the machine by providing system timers, support for the mouse and keyboard, and general-purpose I/O lines for selecting various system functions such as alternate screen and sound buffers and for communicating with the system’s real-time clock and parameter memory.

by Burrell C. Smith

Burrell C. Smith is a member of the Apple Macintosh design team.

Page added on 20th January 2004.

Copyright © 2002-2005 Marcin Wichary
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